1. Field of the Invention
The present invention relates to a new power-gating structure, and in particular to a power-gating structure in which the data stored in volatile memories can be maintained when the system is in a standby mode, and a ground or power supply bounce caused at the switching of a power-gating device can be reduced.
2. Description of the Related Art
As shown in FIG. 1, prior power gating (control) devices can be classified into two, i.e. a footer device and a header device. The footer device is to interpose NMOS sleep transistors between a real ground and a virtual ground; and the header device is to interpose PMOS sleep transistors between a real voltage source (real VDD) and a virtual voltage source (virtual VDD). Moreover, an individual internal circuit can be a combination circuit or a sequential circuit; and the power gating device can receive a sleep signal from a power management unit which determines a current-adopted system power saving scenario. Although the prior power gating control method is practical for the combination circuit, the power gating devices can damage the static noise margin (SNM) of storage elements in the sequential circuit.
FIG. 2 shows a SRAM array having the power gating device. It can be obviously seen from Table 1 that SNM is 0 mV when the power gating device is turned off. It means that the data stored in the SRAM can not be guaranteed to be correct. However, during a standby mode, a 24× leakage current reduction can be achieved by using the prior power gating device.
Many publications propose a resolving scheme by using an MTCMOS as a power gate device. However, in an active mode, a transistor with a much higher threshold voltage used as a power gating device requires a larger silicon area to make the power gating device absorb a maximum instant current. Therefore, it is desired to use a single threshold voltage transistor as a power gating device or to adjust adaptively the well bias of the power gating device for reducing the area occupied by the power gating device.
For example, U.S. Pat. No. 6,552,601, entitled “Method for Supply Gating Low Power Electronic Device” and US Patent Application No. 2003/197544, entitled “Method and Structure for Supply Gated Electronic Components” disclose a power gating device. However, it belongs to a combination of Footer/Header in structure, and still can not be used in memory circuits.
In summary to the above, the prior power gating device has the following disadvantages: 1. a problem of maintaining data retention 2. A problem of reducing ground/power supply bounces caused during switching.